(Preliminary) PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
38MHz<Fout<100MHz
100MHz<Fout<320MHz
65/45/30
80/60/40
3.63
IDD
PECL/LVDS/CMOS
mA
V
VDD
2.97
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
45
45
45
50
50
50
55
55
55
Output Clock
Duty Cycle
%
Short Circuit
Current
mA
±50
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
5. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY
MIN.
TYP.
MAX.
UNITS
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
0.4
0.4
2.5
3
0.5
0.5
4
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
ps
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter RMS
ps
5
4
7
18
20
25
30
30
35
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter Peak-to-
Peak
ps
6. Phase Noise Specifications
@10Hz
@100Hz @1kHz @10kHz @100kHz
@1M
@10M
PARAMETERS
FREQ.
UNITS
77.76MHz
155.52MHz
311.04MHz
-66
-62
-59
-96
-92
-86
-124
-120
-116
-134
-132
-129
-132
-128
-124
-145
-144
-140
-149
-150
-148
Phase Noise
relative to
carrier (typical)
dBc/Hz
Note: Phase Noise measured at VCON = 0V.
7. CMOS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
IOH
IOL
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
30
30
mA
mA
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
0.7
0.3
ns
ns
20%-80% with 50Ω Load
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 5
PLL [ PHASELINK CORPORATION ]
