(Preliminary) PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
FEATURES
PACKAGE PIN ASSIGNMENT
•
•
•
Less than 0.4ps RMS (12KHz-20MHz) phase
VDDANA
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
jitter for all frequencies.
Less than 25ps (typ.) peak to peak jitter for all
frequencies.
Low phase noise output (@ 1MHz frequency
offset
SEL1^
XOUT
GNDBUF
QBAR
SEL2^
OE_CTRL
VCON
GNDANA
LP
VDDBUF
∗
∗
-144dBc/Hz for 155.52MHz
-140dBC/Hz for 311.04MHz
Q
•
•
•
•
•
•
•
•
19MHz-40MHz crystal input.
38MHz-320MHz output.
Available in PECL, LVDS, or CMOS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
GNDBUF
LM
16-pin TSSOP
12 11 10
13
9
4
8
7
6
5
XOUT
SEL2^
GNDBUF
QBAR
VDDBUF
Q
14
15
16
DESCRIPTION
PL580-3X
OE_CTRL
VCON
The PL580-3X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and CMOS, LVDS, or PECL outputs, covering a
wide frequency output range up to 320MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
1
2
3
The frequency selector pads of PL580-3X enable
output frequencies of (2, 4, 8, or 16) * FXIN. The
PL580-3X is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, Video, etc.
3x3 QFN
Note1: QBAR is used for single ended CMOS output.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCON
VCO
Divider
VARICAP
Charge
Output
QBAR
VCO
(FXiNx16)
Pump
XIN
Phase
Detector
XTAL
OSC
Divider
+
Loop
(1,2,4,8)
Q
XOUT
Filter
OE
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 1
PLL [ PHASELINK CORPORATION ]
