(Preliminary) PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
Tri-state
PLL580-38 (PECL)
1
0
Tri-state
PLL580-37 & 39 (CMOS or LVDS)
1 (Default)
Output enabled
PIN DESCRIPTIONS
TSSOP
Pin number
3x3mm QFN
Pin number
Name
Type
Description
VDDANA
XIN
1
2
3
4
5
6
7
11
12
13
14
15
16
1
P
I
VDD for analog Circuitry.
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Output frequency Selector pin.
XOUT
O
I
SEL2
OE_CTRL
VCON
I
Output enable control pin. (See OE_CTRL Logic Levels).
Voltage control input.
I
GNDANA
P
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
LP
8
9
2
3
-
-
LM
GNDBUF
Q
10
11
4
5
P
GND connection for output buffer circuitry.
PECL or LVDS output.
O
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
VDDBUF
12
6
P
QBAR
GNDBUF
SEL1
13
14
15
16
7
8
O
P
I
Complementary PECL, LVDS, Or single ended CMOS output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
9
SEL0
10
I
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 2
PLL [ PHASELINK CORPORATION ]
