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PL580-37QC 参数 Datasheet PDF下载

PL580-37QC图片预览
型号: PL580-37QC
PDF下载: 下载PDF文件 查看货源
内容描述: 38MHz - 320MHz的低相位噪声压控石英振荡器 [38MHz-320MHz Low Phase Noise VCXO]
分类和应用: 振荡器石英晶振压控振荡器
文件页数/大小: 10 页 / 303 K
品牌: PLL [ PHASELINK CORPORATION ]
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(Preliminary) PL580-37/38/39  
38MHz-320MHz Low Phase Noise VCXO  
LAYOUT RECOMMENDATIONS  
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION  
The following guidelines are to assist you with a performance optimized PCB design:  
- Keep all the PCB traces to PL580 as short as  
possible, as well as keeping all other traces as  
far away from it as possible.  
- Place the crystal as close as possible to both  
crystal pins of the device. This will reduce the  
cross-talk between the crystal and the other  
signals.  
- It is highly recommended to keep the VDD and  
GND traces as short as possible.  
- When connecting long traces (> 1 inch) to a  
CMOS output, it is important to design the traces  
as a transmission line or ‘stripline’, to avoid  
reflections or ringing. In this case, the CMOS  
output needs to be matched to the trace  
- Separate crystal pin traces from the other signals  
on the PCB, but allow ample distance between  
the two crystal pin traces.  
- Place a 0.01µF~0.1µF decoupling capacitor  
between VDD and GND, on the component side  
of the PCB, close to the VDD pin. It is not  
recommended to place this component on the  
backside of the PCB. Going through vias will  
reduce the signal integrity, causing additional  
jitter and phase noise.  
impedance. Usually ‘striplines’ are designed for  
50impedance and CMOS outputs usually have  
lower than 50impedance so matching can be  
achieved by adding a resistor in series with the  
CMOS output pin to the ‘stripline’ trace.  
- Please contact PhaseLink for the application note  
on how to design outputs driving long traces or  
the Gerber files for the PL580 layout.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 8