Philips Semiconductors
Preliminary specification
Sound fader control circuit
TEA6320
PINNING
SYMBOL PIN
DESCRIPTION
serial data input/output
SDA
1
2
3
4
5
GND
OUTLR
OUTLF
TL
ground
output left rear
output left front
handbook, halfpage
treble control capacitor left channel or
input from an external equalizer
1
2
32 SCL
SDA
GND
OUTLR
OUTLF
TL
V
31
CC
B2L
6
bass control capacitor left channel or
output to an external equalizer
3
30 OUTRR
29 OUTRF
4
B1L
IVL
7
8
9
bass control capacitor, left channel
input volume I, left control part
input loudness, left control part
5
28
TR
ILL
B2L
6
27 B2R
26 B1R
25 IVR
QSL
IDL
10 output source selector, left channel
11 input D left source
7
B1L
8
IVL
MUTE
ICL
12 mute control
TEA6320
9
24
23
22
21
20
ILR
ILL
QSL
IDL
13 input C left source
14 input mono source
15 input B left source
10
11
12
QSR
IDR
IMO
IBL
IAL
16 input A left source
V
MUTE
ref
IAR
IBR
CAP
ICR
Vref
17 input A right source
18 input B right source
19 electronic filtering for supply
20 input C right source
ICL 13
IMO 14
ICR
19 CAP
IBR
IAR
15
18
17
IBL
IAL 16
21 reference voltage (0.5VCC
22 input D right source
)
MED422
IDR
QSR
ILR
23 output source selector right channel
24 input loudness right channel
IVR
B1R
B2R
25 input volume I, right control part
26 bass control capacitor right channel
27 bass control capacitor right channel or
output to an external equalizer
TR
28 treble control capacitor right channel
or input from an external equalizer
OUTRF
OUTRR
VCC
29 output right front
30 output right rear
31 supply voltage
32 serial clock input
Fig.2 Pin configuration.
SCL
1995 Dec 19
4
NXP [ NXP ]
