Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to
voltage dependent S-distortion in the input stage.
V
OUTA – VOUTB
-------------------------------------------
FEEDB – VOUTB
7. Gv(ol)
=
V
8. Pin FEEDB not connected.
V
FEEDB – V
-------------------------------O----U----T---B-
INA – VINB
9. G V
=
V
10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.
11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.
12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.
13. Measured for REWF = 10 kΩ; REWL = 30 Ω; Vo = 6 V.
a) For Io = 100 mA and a voltage of 9 V at REWL connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is Ii = 300 µA.
b) For Io = 500 mA and a voltage of 21 V at REWL connected to the line output transformer, the east-west amplifier
input current (see Fig.4) is Ii = 350 µA.
1999 Dec 22
9
NXP [ NXP ]
