Philips Semiconductors
Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
TDA8358J
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Flyback switch
Io(peak)
maximum (peak) output current
voltage loss at flyback
t ≤ 1.5 ms
note 11
Io = 1.1 A
−
−
±1.8
A
Vloss(FB)
−
−
7.5
8
8.5
9
V
V
Io = 1.6 A
Guard circuit
VO(grd)
guard output voltage
IO(grd) = 100 µA
5
6
7
V
V
VO(grd)(max) allowable guard voltage
maximum leakage current
−
−
18
IL(max) = 10 µA
IO(grd)
output current
VO(grd) = 0 V; not active
VO(grd) = 4.5 V; active
−
−
−
10
µA
1
2.5
mA
East-west amplifier
Vo
output voltage
at pin OUTEW
−
−
2
−
68
5
V
V
V
Vloss
VI(bias)
II(bias)
voltage loss
Io = 750 mA; note 12
−
input bias voltage
input bias current
2.5
3.2
into pin INEW; note 13
Io = 100 mA
−
−
−
−
−
2.5
11.5
−
−
µA
µA
dB
%
Io = 500 mA
−
Gv(ol)
THD
open-loop voltage gain
harmonic distortion
30
1
0.5
−
f−3dB(h)
high −3 dB cut-off frequency
1
MHz
Notes
1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
and VFB at the first part of the flyback.
2. Allowable input range for both inputs: VI(bias) + Vi(dif)(peak) < 1600 mV and VI(bias) − Vi(dif)(peak) > 100 mV.
3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and
between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value.
4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and
between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value.
5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,
where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum,
maximum and average voltages respectively. The linearity errors are defined as:
Vk – V
a) LE =
b) LE =
k + 1 × 100% (adjacent blocks)
-------------------------
Vavg
V
max – V
min × 100% (non adjacent blocks)
-------------------------------
Vavg
1999 Dec 22
8
NXP [ NXP ]
