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TDA4841PS 参数 Datasheet PDF下载

TDA4841PS图片预览
型号: TDA4841PS
PDF下载: 下载PDF文件 查看货源
内容描述: I2C总线自动同步偏转控制器的PC显示器 [I2C-bus autosync deflection controller for PC monitors]
分类和应用: 显示器消费电路商用集成电路偏转集成电路光电二极管监视器控制器PC
文件页数/大小: 60 页 / 248 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
I2C-bus autosync deflection controller for  
PC monitors  
TDA4841PS  
Start-up procedure  
VCC < 8.3 V:  
START  
As long as the supply voltage is too low for correct  
operation, the IC will give no acknowledge due to  
internal Power-On Reset (POR)  
L1  
L2  
Power-down mode (XXXX XXXX)  
no acknowledge is given by IC  
all register contents are random  
Supply current is 9 mA or less.  
VCC > 8.3 V:  
V
> 8.3 V  
CC  
Internal POR has ended and the IC is in standby mode  
Standby mode (XXXX XX01)  
STDBY = 1  
SOFTST = 0  
all other register contents are random  
Control bits STDBY and SOFTST are reset to their start  
values  
All other register contents are random  
Pin HUNLOCK is at HIGH-level.  
Setting control bit STDBY = 0:  
S
8CH  
A
1AH  
A
00H  
A P  
Enables internal power supply  
Protection mode (XXXX XX00)  
STDBY = 0  
SOFTST = 0  
Supply current increases from 9 to 70 mA  
all other register contents are random  
When VCC < 8.6 V register SOFTST cannot be set by  
the I2C-bus  
Output stages are disabled  
S
8CH  
A
SAD  
A
DATA A P  
Pin HUNLOCK is at HIGH-level.  
Setting all registers to defined values:  
Protection mode (XXXX XX00)  
STDBY = 0  
SOFTST = 0  
registers are pre-set  
Due to the hardware configuration of the IC  
(no auto-increment) any register setting needs a  
complete 3-byte I2C-bus data transfer as follows:  
START - IC address - subaddress - data - STOP.  
no  
all registers defined?  
Setting control bit SOFTST = 1:  
yes  
Before enabling the soft-start sequence a delay of  
minimum 80 ms is necessary to obtain correct function  
of the horizontal drive  
L3  
S
8CH  
A
1AH  
A
02H  
A P  
HDRV duty cycle increases  
BDRV duty cycle increases  
VOUT1 and VOUT2 are enabled  
PLL1 and PLL2 are enabled.  
Soft-start sequence (XXXX XX10)  
STDBY = 0  
SOFTST = 1  
Operating mode (XXXX XX10)  
IC in full operation:  
STDBY = 0  
SOFTST = 1  
Pin HUNLOCK is at LOW-level when PLL1 is locked  
Any change of the register content will result in an  
immediate change of the output behaviour  
no  
no  
change/refresh of data?  
yes  
SOFTST = 0?  
yes  
Setting control bit SOFTST = 0 is the only way (except  
power-down via pin VCC) to leave the operating mode.  
(1)  
L4  
S
8CH  
A
SAD  
A
DATA A P  
MGL791  
Soft-down sequence:  
See L4 of Fig.19 for starting the soft-down sequence.  
(1) See Fig.19.  
Fig.18 I2C-bus flow for start-up.  
1999 Oct 25  
38  
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