Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
handbook, full pagewidth
(ANY Mode)
V
< 8.1 V
CC
Power-Down Mode
V
a soft-down sequency followed by a
soft start sequence is generated
internally.
no acknowledge is given by IC
all register contents are random
CC
8.6 V
8.1 V
V
IC enters standby mode.
CC
8.6 V
8.1 V
(1)
L1
MGM079
(1) See Fig.18.
Fig.20 I2C-bus flow for any mode.
Power-down mode
Power dip of VCC < 8.6 V:
Normal operation
• The soft-down sequence is started first
• Then the soft-start sequence is generated internally.
2
I C-bus transmission
Power dip of VCC < 8.1 V or VCC shut-down:
chip address
subaddress
0XH
data
S
8CH
A
A
XXH
A
P
• This function is independent from the operating mode,
therefore it works under any condition
• All driver outputs are immediately disabled
• IC enters standby mode.
yes
acknowledge was
given on data?
Standby mode detection
no
2
Execute data transmission twice to assure that there was
no data transfer error.
I C-bus transmission
subaddress
chip address
8CH
data
XXH
S
A
0XH
A
A
P
yes
acknowledge was
given on data?
no
Standby mode
MGS276
Fig.21 Possible standby mode detection.
1999 Oct 25
40
NXP [ NXP ]
