Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
List of I2C-bus controlled switches
I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress:
• SAD1 is the register subaddress to be used for transmissions in direct mode
• SAD2 is the register subaddress to be used for transmissions in buffered mode.
Table 5 Controlled switches; notes 1 and 2
REGISTER ASSIGNMENT
CONTROL
BIT
SAD1 SAD2
(HEX) (HEX)
FUNCTION
D7 D6 D5 D4 D3 D2 D1 D0
BLKDIS
0: vertical, protection and horizontal unlock
0A
8A
X
D6
#
#
#
#
#
#
blanking available on pins CLBL and HUNLOCK
1: only vertical and protection blanking available
on pins CLBL and HUNLOCK
AGCDIS
FHMULT
0: AGC in vertical oscillator active
1: AGC in vertical oscillator inhibited
0B
0B
8B
8B
#
D6
#
#
#
#
#
#
#
#
#
#
#
#
#
0: EW output independent of horizontal
frequency
D7
1: EW output tracks with horizontal frequency
VSC
0: VLIN, HCORT and HCORB adjustments
enabled
02
08
82
88
X
D6
#
#
#
#
#
#
#
#
#
#
#
#
#
1: VLIN, HCORT and HCORB adjustments
forced to centre value
MOD
0: horizontal and vertical moire cancellation
enabled
D7
1: horizontal and vertical moire cancellation
disabled
VOVSCN
CLAMP
VBLK
0: vertical size 100%
0F
09
09
04
1A
1A
8F
89
89
84
9A
9A
X
#
D6
D6
#
#
#
#
#
X
X
#
#
#
#
X
X
#
#
#
#
X
X
#
#
#
#
X
X
#
#
#
#
1: vertical size 116.8% for VGA350
0: trailing edge for horizontal clamp
1: leading edge for horizontal clamp
0: vertical blanking = 260 µs
D7
X
#
#
1: vertical blanking = 340 µs
ACD
0: ASCOR disconnected from PLL2
1: ASCOR internally connected with PLL2
0: internal power supply enabled
1: internal power supply disabled
D6
X
#
#
STDBY(3)
#
#
D0
#
SOFTST(3) 0: soft start not released (pin HPLL2 pulled to
ground)
#
X
D1
1: soft start is released (power-up via pin HPLL2)
Notes
1. X = don’t care.
2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be
transferred.
3. Bits STDBY and SOFTST can be reset by the internal protection circuit.
1999 Oct 25
35
NXP [ NXP ]
