Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for
PC monitors
TDA4841PS
Soft-start and soft-down sequences
handbook, full pagewidth
MHB495
V
HPLL2
4.6 V continuous blanking off
PLL2 enabled
frequency detector enabled
HDRV/HFLB protection enabled
4.0 V BDRV duty cycle has reached nominal value
3.2 V BDRV duty cycle begins to increase
HDRV duty cycle has reached nominal value
1.8 V
1.0 V
HDRV duty cycle begins to increase
VOUT1 and VOUT2 enabled
time
a. Soft-start sequence for VCC > 8.6 V.
handbook, full pagewidth
MHB496
V
HPLL2
4.6 V continuous blanking (pin 16 and 17) activated
PLL2 disabled
frequency detector disabled
HDRV/HFLB protection disabled
(1)
4.0 V BDRV duty cycle begins to decrease
2.8 V BDRV floating
(1)
HDRV duty cycle begins to decrease
1.8 V HDRV floating
1.0 V VOUT1 and VOUT2 floating
time
b. Soft-down sequence for VCC > 8.6 V.
(1) Pins HDRV and BDRV are floating for VCC < 8.6 V.
Fig.23 Activation of PLL2 soft-start and soft-down sequences via the I2C-bus.
1999 Oct 25
42
NXP [ NXP ]
