Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 53 Field interval definitions for D1 (CCIR 656) SAV and EAV codes; note 1
DEFINITION
625 LINES
525 LINES
V-digital field blanking
Field 1; start (V = 1)
Field 1; finish (V = 0)
Field 2; start (V = 1)
Field 2; finish (V = 0)
Line 624
Line 23
Line 1
Line 10
Line 264
Line 273
Line 311
Line 336
F-digital field identification
Field 1; F = 0
Field 2; F = 1
Line 1
Line 4
Line 313
Line 266
Note
1. Signals F and V change state synchronously with the end of active video timing reference code at the beginning of
the digital line.
7.8.6.1
Field detection control
Field detection modes:
• Direct mode: FLD signal detected from incoming H/V signals, for timing behaviour see Fig.11.
• Forced toggle: FLD signal regularly synchronized to source, but will never stay more than two fields with the same ID.
The circuit expects to detect a field change with every vertical reference edge, if the field does not change (field error),
the circuit change the field ID automatically. If the circuit switch to the wrong sequence i. e. at the beginning of
processing, it will be synchronized after one second where no field error has occurred.
• Free toggle: FLD signal toggles with every vertical reference edge, independent of source FID.
handbook, full pagewidth
LLC
HS
VS
FLD
V-DMSD
FLD-DMSD
MHB053
Fig.12 Timing of field detection EVEN-to-ODD for direct mode.
1998 Apr 09
61
NXP [ NXP ]
