Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 54 Offsets to CCIR 656 line 23 depending on PAL or NTSC source (in compliance with Recommendation 601),
ODD and EVEN field and select mode (see note 1)
PAL
NTSC
SLC(4)
FALLING
VS
SLC
FALLING
VS
SLC(2)
SAV/EAV
SLC ext.(3)
SLC(5)
RISING VS
SLC
SAV/EAV
SLC ext.
FS
SLC
RISING VS
FS
24 (25)
15 (16)
15H (16)
21 (22)
22 (22)
12 (13))
12 (13)
18 (19)
18H (19H)
0FH (10H)
0FH (10H)
15H (16H)
16H (16H)
0CH (0DH)
0CH (0DH)
12H (13H)
Notes
1. Line numbers in parenthesis refer to EVEN field counting.
2. Sync signal SLC with SAV/EAV detection (50H, SYNC_X = 7).
3. Sync signal SLC with external Field Identification Signal (50H, SYNC_X = 6).
4. Sync signal SLC with detection on the falling edge of the vertical sync signal (50H, SYNC_X = 1, 3 or 5).
5. Sync signal SLC with detection on the rising edge of the vertical sync signal. For Philips devices, the rising edge does
not include field information, this information is only defined at the falling edge of the VS signal (50H, SYNC_X = 0, 2
or 4).
7.8.8.1
Video with PAL format
handbook, full pagewidth
FID CCIR 656
VS CCIR 656
ODD SAA711x
VS SAA711x
(1)
LINES
308
309
310
311
312
313
314
(1)
315
(2)
316
(3)
317
(4)
318
(5)
319
(6)
320
(7)
321
(8)
(2)
(308)
(309)
(310)
(311)
(312)
(313)
MHB057
(1) The line numbers not in parenthesis refer to CCIR counting.
(2) The line numbers in parenthesis refer to single field counting.
Fig.15 Output timing of SAA711x, 50 Hz, lines 621 to 8.
1998 Apr 09
64
NXP [ NXP ]
