Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
HS_x
handbook, full pagewidth
PXQ_x
ACTIVE VIDEO WINDOW
NumBytes
HXO
BXO
field/
frame
SCALING
WINDOW
MHB055
line
(1) LQ = qualified lines, i.e. lines containing at least one qualified pixel.
Fig.14 Reference signals for scaling window.
7.8.8
COMPARISON BETWEEN CCIR 656 LINE AND SOURCE LINE COUNTER
This section describes how to choose the vertical offset and how to use the source line counter event for RPS
programming for capturing the expected line.
The internal Source Line Counter (SLC) is reset by the selected edge of the vertical sync signal which is provided at port
VS_x. The falling and rising edges of this signal are selected by the SYNC_X bits in the ‘Initial settings DD1 Port Register’
(offset = 50H). Consequently, the behaviour of the SLC depends on the connected vertical sync signal so that different
offsets must be selected to capture the expected line. The active video begins in the CCIR 656 line 23 of the video signal;
Table 54 lists the different offsets which must be selected to capture the expected line. The subsequent diagrams and
tables illustrate the relationship between the different vertical sync signals of the PAL and NTSC standards, the ODD and
EVEN field and the internal SLC.
1998 Apr 09
63
NXP [ NXP ]
