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SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
(1)
Header and data identification
(DID) code control
5D
FVREF
DID5
DID4
DID3
DID2
DID1
DID0
(1)
(1)
Sliced data identification (SDID)
code
5E
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
5F
60
Slicer status byte 0 (read only)
Slicer status byte 1 (read only)
Slicer status byte 2 (read only)
Reserved
−
−
FC8V
FC7V
VPSV
LN8
PPV
LN7
CCV
LN6
−
−
61
−
F21_N
LN5
LN4
62
LN3
(1)
LN2
(1)
LN1
(1)
LN0
(1)
DT3
(1)
DT2
(1)
DT1
(1)
DT0
(1)
63 to 7F
X-port, I-port and the scaler part: registers 80H to EFH
TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH
(1)
Global control 1
Reserved
80
SMOD
(1)
TEB
(1)
TEA
(1)
ICKS3
(1)
ICKS2
(1)
ICKS1
(1)
ICKS0
(1)
(1)
81 and
82
(1)
(1)
(1)
X-port I/O enable and output
clock phase control
83
XPCK1
XPCK0
XRQT
XPE1
XPE0
I-port signal definitions
I-port signal polarities
84
85
86
IDG01
ISWP1
VITX1
IDG00
ISWP0
VITX0
IDG11
ILLV
IDG10
IG0P
IDV1
IG1P
FFL1
IDV0
IRVP
FFL0
IDH1
IRHP
FEL1
IDH0
IDQP
FEL0
I-port FIFO flag control and
arbitration
IDG02
IDG12
(1)
(1)
I-port I/O enable, output clock
and gated clock phase control
87
IPCK3
IPCK2
IPCK1
IPCK0
IPE1
IPE0
(1)
(1)
Power save control
Reserved
88
89 to 8E
8F
CH4EN
CH2EN
SWRST
DPROG
SLM3
(1)
SLM1
(1)
SLM0
(1)
(1)
(1)
(1)
(1)
Status information scaler part
XTRI
ITRI
FFIL
FFOV
PRDON
ERR_OF
FIDSCI
FIDSCO
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window definition
Task handling control
90
91
92
CONLH
CONLV
XFDV
OFIDC
HLDFV
XFDH
FSKP2
SCSRC1
XDV1
FSKP1
SCSRC0
XDV0
FSKP0
SCRQE
XCODE
RPTSK
FSC2
XDH
STRC1
FSC1
XDQ
STRC0
FSC0
X-port formats and configuration
X-port input reference signal
definition
XCKS
NXP [ NXP ]
