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Table 36 I2C-bus receiver/transmitter overview
SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Chip version: register 00H
Chip version (read only)
00
ID07
ID06
ID05
ID04
−
−
−
−
Video decoder: registers 01H to 2FH
FRONT-END PART: REGISTERS 01H TO 05H
(1)
(1)
(1)
(1)
Horizontal increment delay
Analog input control 1
Analog input control 2
Analog input control 3
Analog input control 4
01
02
03
04
05
IDEL3
MODE3
HOLDG
GAI13
IDEL2
MODE2
GAFIX
GAI12
GAI22
IDEL1
MODE1
GAI28
GAI11
GAI21
IDEL0
MODE0
GAI18
GAI10
GAI20
FUSE1
FUSE0
HLNRS
GAI16
GAI26
GUDL1
VBSL
GUDL0
WPOFF
GAI14
(1)
GAI17
GAI27
GAI15
GAI25
GAI24
GAI23
DECODER PART: REGISTERS 06H TO 2FH
Horizontal sync start
Horizontal sync stop
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
HSB7
HSS7
HSB6
HSS6
HSB5
HSS5
HSB4
HSS4
HSB3
HSS3
HSB2
HSS2
HSB1
HSS1
HSB0
HSS0
Sync control
AUFD
FSEL
FOET
HTC1
HTC0
HPLL
VNOI1
LUFI1
DBRI1
DCON1
DSAT1
VNOI0
LUFI0
Luminance control
BYPS
YCOMB
DBRI6
DCON6
DSAT6
HUEC6
CSTD2
CGAIN6
OFFU0
RTP1
LDEL
LUBW
LUFI3
LUFI2
Luminance brightness control
Luminance contrast control
Chrominance saturation control
Chrominance hue control
Chrominance control 1
Chrominance gain control
Chrominance control 2
Mode/delay control
DBRI7
DCON7
DSAT7
HUEC7
CDTO
ACGC
OFFU1
COLO
RTSE13
RTCE
DBRI5
DCON5
DSAT5
HUEC5
CSTD1
CGAIN5
OFFV1
HDEL1
RTSE11
XRVS1
AOSL1
DBRI4
DCON4
DSAT4
HUEC4
CSTD0
CGAIN4
OFFV0
HDEL0
RTSE10
XRVS0
AOSL0
DBRI3
DCON3
DSAT3
HUEC3
DCVF
DBRI2
DCON2
DSAT2
HUEC2
FCTC
DBRI0
DCON0
DSAT0
HUEC0
CCOMB
CGAIN0
LCBW0
YDEL0
RTSE00
OFTS0
APCK0
HUEC1
(1)
CGAIN3
CHBW
RTP0
CGAIN2
LCBW2
YDEL2
RTSE02
OFTS2
OLDSB
CGAIN1
LCBW1
YDEL1
RTSE01
OFTS1
APCK1
RT signal control
RTSE12
XRHS
RTSE03
HLSEL
XTOUTE
RT/X-port output control
Analog/ADC/compatibility
control
CM99
UPTCV
VGATE start, FID change
VGATE stop
15
16
17
VSTA7
VSTO7
LLCE
VSTA6
VSTO6
LLC2E
VSTA5
VSTA4
VSTA3
VSTA2
VSTO2
VGPS
VSTA1
VSTO1
VSTO8
VSTA0
VSTO0
VSTA8
VSTO5
VSTO4
VSTO3
(1)
(1)
(1)
Miscellaneous/VGATE MSBs
NXP [ NXP ]
