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SUB
REGISTER FUNCTION
Reserved
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
DB
DC
DD
DE
Horizontal chrominance scaling
increment
XSCC7
XSCC6
XSCC5
XSCC4
XSCC12
XPHC4
XSCC3
XSCC11
XPHC3
XSCC2
XSCC10
XPHC2
XSCC1
XSCC9
XPHC1
XSCC0
XSCC8
XPHC0
(1)
(1)
(1)
Horizontal chrominance phase
offset
XPHC7
XPHC6
XPHC5
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
DF
Vertical scaling
Vertical luminance scaling
increment
E0
E1
YSCY7
YSCY15
YSCC7
YSCY6
YSCY14
YSCC6
YSCY5
YSCY13
YSCC5
YSCY4
YSCY12
YSCC4
YSCC12
YSCY3
YSCY11
YSCC3
YSCY2
YSCY10
YSCC2
YSCY1
YSCY9
YSCC1
YSCY0
YSCY8
YSCC0
YSCC8
Vertical chrominance scaling
increment
E2
E3
YSCC15
YSCC14
YSCC13
YSCC11
YSCC10
YSCC9
(1)
(1)
(1)
(1)
(1)
(1)
Vertical scaling mode control
Reserved
E4
YMIR
(1)
YMODE
(1)
(1)
(1)
(1)
(1)
(1)
(1)
E5 to E7
E8
Vertical chrominance phase
offset ‘00’
YPC07
YPC06
YPC05
YPC04
YPC14
YPC24
YPC34
YPY04
YPY14
YPY24
YPY34
YPC03
YPC02
YPC01
YPC00
YPC10
YPC20
YPC30
YPY00
YPY10
YPY20
YPY30
Vertical chrominance phase
offset ‘01’
E9
EA
EB
EC
ED
EE
EF
YPC17
YPC27
YPC37
YPY07
YPY17
YPY27
YPY37
YPC16
YPC26
YPC36
YPY06
YPY16
YPY26
YPY36
YPC15
YPC25
YPC35
YPY05
YPY15
YPY25
YPY35
YPC13
YPC23
YPC33
YPY03
YPY13
YPY23
YPY33
YPC12
YPC22
YPC32
YPY02
YPY12
YPY22
YPY32
YPC11
YPC21
YPC31
YPY01
YPY11
YPY21
YPY31
Vertical chrominance phase
offset ‘10’
Vertical chrominance phase
offset ‘11’
Vertical luminance phase
offset ‘00’
Vertical luminance phase
offset ‘01’
Vertical luminance phase
offset ‘10’
Vertical luminance phase
offset ‘11’
Note
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
NXP [ NXP ]
