Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
Table 34 Description of I2C-bus format
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
Slave address W
Slave address R
ACK-s
‘0100 0010’ (= 42H, default) or ‘0100 0000’ (= 40H; note 1)
‘0100 0011’ (= 43H, default) or ‘0100 0001’ (= 41H; note 1)
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
Subaddress
Data
subaddress byte; see Tables 35 and 36
data byte; see Table 36; if more than one byte DATA is transmitted the subaddress pointer is
automatically incremented
P
X
STOP condition
read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)
Note
1. If pin RTCO strapped to ground via a 3.3 kΩ resistor.
Table 35 Subaddress description and access
SUBADDRESS
00H
F0H to FFH
DESCRIPTION
ACCESS (READ/WRITE)
chip version
reserved
read only
−
Video decoder: 01H to 2FH
01H to 05H
06H to 19H
1AH to 1EH
1FH
front-end part
read and write
decoder part
reserved
read and write
−
read only
−
video decoder status byte
reserved
20H to 2FH
Audio clock generation: 30H to 3FH
30H to 3AH
3BH to 3FH
audio clock generator
reserved
read and write
−
General purpose VBI-data slicer: 40H to 7FH
40H to 60H
61H to 62H
64H to 7FH
VBI-data slicer
VBI-data slicer status
reserved
read and write
read only
−
X-port, I-port and the scaler: 80H to EFH
80H to 8FH
90H to BFH
C0H to EFH
task independent global settings
read and write
read and write
read and write
task A definition
task B definition
2000 Mar 15
81
NXP [ NXP ]
