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SUB
REGISTER FUNCTION
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Raw data gain control
Raw data offset control
Reserved
18
19
RAWG7
RAWG6
RAWG5
RAWG4
RAWG3
RAWG2
RAWG1
RAWG0
RAWO7
RAWO6
RAWO5
RAWO4
RAWO3
RAWO2
RAWO1
RAWO0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1A to 1E
1F
Status byte video decoder
(read only, OLDSB = 0)
INTL
HLVLN
FIDT
GLIMT
GLIMB
WIPA
COPRO
RDCAP
Status byte video decoder
(read only, OLDSB = 1)
1F
INTL
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
20 to 2F
Audio clock generator part: registers 30H to 3FH
Audio master clock cycles per
field
30
31
ACPF7
ACPF6
ACPF5
ACPF4
ACPF3
ACPF2
ACPF1
ACPF9
ACPF0
ACPF8
ACPF15
ACPF14
ACPF13
ACPF12
ACPF11
ACPF10
(1)
(1)
(1)
(1)
(1)
(1)
32
ACPF17
ACPF16
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
33
Audio master clock nominal
increment
34
ACNI7
ACNI6
ACNI5
ACNI4
ACNI3
ACNI2
ACNI1
ACNI9
ACNI0
ACNI8
35
ACNI15
ACNI14
ACNI13
ACNI12
ACNI11
ACNI10
(1)
(1)
36
ACNI21
ACNI20
ACNI19
ACNI18
ACNI17
ACNI16
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved
37
Clock ratio AMCLK to ASCLK
Clock ratio ASCLK to ALRCLK
Audio clock control
Reserved
38
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
39
LRDIV5
LRDIV4
LRDIV3
LRDIV2
LRDIV1
LRDIV0
(1)
(1)
3A
APLL
(1)
AMVR
(1)
LRPH
(1)
SCPH
(1)
(1)
(1)
3B to 3F
General purpose VBI-data slicer part: registers 40H to 7FH
(1)
(1)
(1)
(1)
(1)
Slicer control 1
40
41 to 57
58
HAM_N
LCRn_6
FC6
FCE
LCRn_5
FC5
HUNT_N
LCRn_4
FC4
LCR2 to LCR24 (n = 2 to 24)
Programmable framing code
Horizontal offset for slicer
Vertical offset for slicer
LCRn_7
FC7
LCRn_3
FC3
LCRn_2
FC2
LCRn_1
FC1
LCRn_0
FC0
59
HOFF7
VOFF7
FOFF
HOFF6
VOFF6
RECODE
HOFF5
HOFF4
VOFF4
VOFF8
HOFF3
HOFF2
VOFF2
HOFF10
HOFF1
VOFF1
HOFF9
HOFF0
VOFF0
HOFF8
5A
VOFF5
VOFF3
(1)
(1)
Field offset and MSBs for
5B
horizontal and vertical offset
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Reserved (for testing)
5C
NXP [ NXP ]
