Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
handbook, full pagewidth
625
312
1
1
2
2
3
3
4
4
5
5
6
6
7
7
22
22
23
23
624
311
...
...
ITU counting
622
309
623
310
single field counting
CVBS
HREF
F_ITU656
(1)
V123
[
]
VSTO 8:0 = 134H
VGATE
FID
[
]
VSTA 8:0 = 15H
(a) 1st field
312
312
313
313
314
1
315
2
316
3
317
4
318
5
319
6
335
22
336
23
ITU counting
single field counting
311
311
309
309
310
310
...
...
CVBS
HREF
F_ITU656
(1)
V123
[
]
VSTO 8:0 = 134H
VGATE
FID
(b) 2nd field
[
]
VSTA 8:0 = 15H
MHB540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME
HREF
RTS0 (PIN 34) RTS1 (PIN 35) XRH (PIN 92) XRV (PIN 91)
X
−
X
−
X
−
−
−
−
F_ITU656
V123
X
X
X
X
X
X
X
X
VGATE
FID
−
For further information see Section 15.2: Tables 55, 56 and 57.
Fig.21 Vertical timing diagram for 50 Hz/625 line systems.
34
2000 Mar 15
NXP [ NXP ]
