Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
8.3
Scaler
The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relations. With a safety margin of
2% for running in and running out, the maximum
HV_zoom is equal to:
The High Performance video Scaler (HPS) is based on the
system as implemented in SAA7140, but enhanced in
some aspects. Vertical upsampling is supported and the
processing pipeline buffer capacity is enhanced, to allow
more flexible video stream timing at the image port,
discontinuous transfers, and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process itself.
T_input_field – T_v_blanking
in_pixel × in_lines × out_cycle_per_pix × T_out_clk
0.98 ×
-------------------------------------------------------------------------------------------------------------------------------------
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit
data at 13.5 MHz data rate, 1 cycle per pixel;
output: 8-bit data at 27 MHz, 2 cycles per pixel;
the maximum HV_zoom is equal to:
The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks. Therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.
20 ms – 24 × 64 µs
720 × 288 × 2 × 37 ns
0.98 ×
= 1.18
--------------------------------------------------------
2. Input from X-port: 60 Hz, 720 pixel, 240 lines, 8-bit
data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H-port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
The high performance video scaler in SAA7114H has the
following major blocks.
• Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)
16.666 ms – 22 × 64 µs
720 × 240 × 1 × 37 ns
0.98 ×
= 2.34
--------------------------------------------------------------
• Prescaler, for horizontal down-scaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format
The video scaler receives its input signal from the video
decoder or from the expansion port (X-port).
It gets 16-bit YUV 4 : 2 : 2 input data at a continuous rate
of 13.5 MHz from the decoder. Discontinuous data stream
can be accepted from the expansion port (X-port),
normally 8-bit wide ITU 656 like YUV data, accompanied
by a pixel qualifier on XDQ.
• Brightness, saturation, contrast control for scaled output
data
• Line buffer, with asynchronous read and write, to
support vertical up-scaling (e.g. for videophone
application, converting 240 into 288 lines, YUV 4 : 2 : 2)
The input data stream is sorted into two data paths, one for
luminance (or raw samples), and one for time multiplexed
chrominance U and V samples. An YUV 4 : 1 : 1 input
format is converted to 4 : 2 : 2 for the horizontal prescaling
and vertical filter scaling operation.
• Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and down-scale, or phase
accurate Accumulation Mode (ACM) for large
down-scaling ratios and better alias suppression
• Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
(SQR) and rectangular (CCIR) pixel sampling
The scaler operation is defined by two programming
pages A and B, representing two different tasks, that can
be applied field alternating or to define two regions in a
field (e.g. with different scaling range, factors, and signal
source during odd and even fields).
• Output formatter for scaled YUV 4 : 2 : 2, YUV 4 : 1 : 1
and Y only (format also for raw data)
Each programming page contains control:
• For signal source selection and formats
• For task handling and trigger conditions
• For input and output acquisition window definition
• For H-prescaler, V-scaler and H-phase scaling.
• FIFO, 32-bit wide, with 64 pixel capacity in YUV formats
• Output interface, 8 or 16 (only if extended by H-port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.
2000 Mar 15
37
NXP [ NXP ]
