Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
handbook, full pagewidth
burst
CVBS input
processing delay ADC to expansion port:
140 × 1/LLC
expansion port
data output
sync clipped
HREF (50 Hz)
12 × 2/LLC
144 × 2/LLC
720 × 2/LLC
5 × 2/LLC
CREF
CREF2
2 × 2/LLC
HS (50 Hz)
programming range
(step size: 8/LLC)
−107
108
0
HREF (60 Hz)
16 × 2/LLC
138 × 2/LLC
720 × 2/LLC
1 × 2/LLC
CREF
CREF2
HS (60 Hz)
2 × 2/LLC
−106
programming range
(step size: 8/LLC)
107
0
MHB542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 55 and 56);
their polarity can be inverted via RTP0 and/or RTP1.
The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 57).
Fig.23 Horizontal timing diagram (50/60 Hz).
2000 Mar 15
36
NXP [ NXP ]
