Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
8.1.4
SYNCHRONIZATION
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is further reduced to
1 MHz in a low-pass filter. The sync pulses are sliced and
fed to the phase detectors where they are compared with
the sub-divided clock frequency. The resulting output
signal is applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO,
see Fig.19.
6.75 MHz = 429 × fH (50 Hz), or
6.75 MHz = 432 × fH (60 Hz).
Internally the LFCO signal is multiplied by a factor of
2 and 4 in the PLL circuit (including phase detector, loop
filtering, VCO and frequency divider) to obtain the output
clock signals. The rectangular output clocks have a 50%
duty factor.
Table 2 Decoder clock frequencies
The detection of ‘pseudo syncs’ as part of the macrovision
copy protection standard is also done within the
synchronization circuit.
CLOCK
FREQUENCY (MHz)
XTALO
LLC
24.576 or 32.110
27
The result is reported as flag COPRO within the decoder
status byte at subaddress 1FH.
LLC2
13.5
6.75
3.375
LLC4 (internal)
LLC8 (virtual)
8.1.5
CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
handbook, full pagewidth
ZERO
BAND PASS
PHASE
DETECTION
LOOP
FILTER
CROSS
LFCO
OSCILLATOR
LLC
FC = LLC/4
DETECTION
DIVIDER
1/2
DIVIDER
1/2
LLC2
MHB330
Fig.19 Block diagram of the clock generation circuit.
8.1.6
POWER-ON RESET AND CHIP ENABLE (CE) INPUT
It is possible to force a reset by pulling the Chip Enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA
return from 3-state to active, while the other signals have
to be activated via programming.
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.7 V) will start the reset sequence; all
outputs are forced to 3-state (see Fig.20). The indicator
output RES is LOW for about 128 LLC after the internal
reset and can be applied to reset other circuits of the digital
TV system.
2000 Mar 15
30
NXP [ NXP ]
