Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
handbook, full pagewidth
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
21
21
22
22
2
2
...
...
ITU counting
525
262
1
1
single field counting
CVBS
HREF
F_ITU656
(1)
V123
[
]
VSTO 8:0 = 101H
VGATE
FID
[
]
VSTA 8:0 = 011H
(a) 1st field
265
2
266
3
267
4
268
5
269
6
270
7
271
8
272
9
284
21
285
22
ITU counting
single field counting
264
1
262
262
263
263
...
...
CVBS
HREF
F_ITU656
(1)
V123
[
]
VSTO 8:0 = 101H
VGATE
FID
(b) 2nd field
[
]
VSTA 8:0 = 011H
MHB541
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME
HREF
RTS0 (PIN 34) RTS1 (PIN 35) XRH (PIN 92) XRV (PIN 91)
X
−
X
−
X
−
−
−
−
−
X
X
−
−
F_ITU656
V123
X
X
X
X
X
X
VGATE
FID
For further information see Section 15.2: Tables 55, 56 and 57.
Fig.22 Vertical timing diagram for 60 Hz/525 line systems.
35
2000 Mar 15
NXP [ NXP ]
