Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.23 SUBADDRESS 17H
Table 54 VGATE MSBs
FUNCTION
LOGIC LEVEL
CONTROL BIT
VSTA8, see SA 15
MSB VGATE start
VSTO8, see SA 16
MSB VGATE stop
see Table 52
see Table 53
D0
D1
15.2.24 SUBADDRESS 1FH (READ ONLY REGISTER)
Table 55 Status byte video decoder SA 1F
I2C-BUS
CONTROL BIT
FUNCTION
ready for capture (all internal loops locked); active HIGH (OLDSB = 0)
DATA BIT
RDCAP
CODE
D0
colour signal in accordance with selected standard has been detected; active HIGH
(OLDSB = 1)
COPRO
copy protected source detected according to macrovision version up to 7.01
(OLDSB = 0)
D1
SLTCA
WIPA
slow time constant active in WIPA mode; active HIGH (OLDSB = 1)
white peak loop is activated; active HIGH
D2
D3
D4
D5
D6
GLIMB
GLIMT
FIDT
gain value for active luminance channel is limited [min (bottom)]; active HIGH
gain value for active luminance channel is limited [max (top)]; active HIGH
identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz
status bit for horizontal/vertical loop: LOW = locked, HIGH = unlocked (OLDSB = 0)
HLVLN
HLCK
status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked
(OLDSB = 1)
INTL
status bit for interlace detection; LOW = non-interlaced, HIGH = interlaced
D7
15.2.25 SUBADDRESS 40H
Table 56 Data slicer clock selection
SLICER SET (40H)
CONTROL BITS D2 AND D1
CLKSEL1 CLKSEL0
AMPLITUDE SEARCHING
Reserved
13.5 MHz (default)
Reserved
00
01
10
11
Reserved
Table 57 Amplitude searching
SLICER SET (40H)
CONTROL BIT D4
HUNT_N
AMPLITUDE SEARCHING
Amplitude searching active (default)
0
1
Amplitude searching stopped
1999 Jul 01
68
NXP [ NXP ]
