Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
handbook, full pagewidth
CVBS input
burst
28 × 1/LLC
burst
RAW DATA on VPO-bus
157 × 1/LLC
(2)
processing delay CVBS->VPO
Y-DATA on VPO-bus
RTS0/1 HREF (50 Hz)
0
sync clipped
12 × 2/LLC
144 × 2/LLC
720 × 2/LLC
15 × 2/LLC
55 × 2/LLC
(1)
RTS0/1 (PLIN)
4/LLC
RTS0/1 HS
RTS0/1 HS (50 Hz)
programming range
(step size: 8/LLC)
−107
108
0
RTS0/1 HREF (60 Hz)
11 × 2/LLC
16 × 2/LLC
138 × 2/LLC
720 × 2/LLC
RTS0/1 HS (60 Hz)
RTS0/1 HS (60 Hz)
programming range
(step size: 8/LLC)
107
−106
0
MHB335
(1) PLIN is switched to outputs RTS0 and/or RTS1 via I2C-bus bits RTSE13 to RTSE10 and/or RTSE03 to RTSE00.
(2) See Table 21.
Fig.28 Horizontal timing diagram.
1999 Jul 01
42
NXP [ NXP ]
