Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
handbook, full pagewidth
625
1
2
3
4
5
6
7
8
22
23
622
623
624
input CVBS
RTS0/1 HREF
RTS0/1 VREF
(1)
VRLN = 1
RTS0/1 VREF
(1)
VRLN = 0
499 × 2/LLC
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
(3)
(2)
RTS0/1 FID
(a) 1st field
310
312
315
316
318
319
320
335
336
337
313
314
317
311
input CVBS
RTS0/1 HREF
RTS0/1 VREF
(1)
VRLN = 1
RTS0/1 VREF
(1)
VRLN = 0
67 × 2/LLC
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
(3)
(2)
RTS0/1 FID
MHB336
(b) 2nd field
HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.
ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.
VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = BH.
V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.
VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.
FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.
(1) VREF range short or long can be programmed via I2C-bus bit VRLN.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
(2) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.
(3) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the
field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of the slope is dependent on the
internal processing delay and may change a few clock cycles from version to version.
Fig.29 Vertical timing diagram for 50 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR
or fast mode (HTC = 01 or 11)].
1999 Jul 01
43
NXP [ NXP ]
