Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs
VIL(SCL,SDA)
LOW-level input voltage
pins SDA and SCL
−0.5
−
−
−
−
−
−
+0.3VDDD
VDDD + 0.5
+0.8
V
VIH(SCL,SDA)
VIL(xtal)
VIH(xtal)
VIL(n)
HIGH-level input voltage
pins SDA and SCL
0.7VDDD
−0.3
2.0
V
V
V
V
V
LOW-level CMOS input
voltage pin XTALI
HIGH-level CMOS input
voltage pin XTALI
VDDD + 0.3
+0.8
LOW-level input voltage all
other inputs
−0.3
2.0
VIH(n)
HIGH-level input voltage
all other inputs
5.5
ILI
input leakage current
input capacitance
−
−
−
−
−
−
10
8
µA
pF
pF
Ci
outputs at 3-state
Ci(n)
input capacitance all other
inputs
5
Digital outputs
VOL(SCL,SDA) LOW-level output voltage SDA/SCL at 3 mA (6 mA)
pins SDA and SCL sink current
−
−
0.4 (0.6)
V
VOL
LOW-level output voltage VDDD = max; IOL = 2 mA
0
−
−
−
0.4
V
V
V
VOH
HIGH-level output voltage VDDD = min; IOH = −2 mA
2.4
−0.5
VDDD + 0.5
+0.6
VOL(clk)
LOW-level output voltage
for LLC clock
VOH(clk)
HIGH-level output voltage
for LLC clock
2.4
−
VDDD + 0.5
V
RTS1 (DOT) input timing
tSU;DAT input data set-up time
tHD;DAT input data hold time
Data and control output timing; note 1
13
3
−
−
−
−
ns
ns
CL
output load capacitance
output hold time
15
4
−
−
−
−
40
−
pF
ns
ns
ns
tOHD;DAT
tPD
CL = 15 pF
CL = 25 pF
propagation delay
−
22
22
tPDZ
propagation delay to
3-state
−
1999 Jul 01
38
NXP [ NXP ]
