Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
525
(3)
1
(4)
2
(5)
3
(6)
4
(7)
5
(8)
6
(9)
7
(10)
17
(20)
18
(21)
19
(22)
handbook, full pagewidth
input CVBS
524
(2)
522
(525)
523
(1)
8
(11)
(1)
RST0/1 HREF
(2)
VRLN = 1
RTS0/1 VREF
RTS0/1 VREF
(2)
VRLN = 0
520 × 2/LLC
RTS0/1 VS
RTS0/1 ODD
(4)
RTS0/1 V123
(3)
RTS0/1 FID
(a) 1st field
260
(263)
263
264
265
266
267
268
269
270
271
262
280
281
259
(262)
282
261
(264)
(1)
(265) (266) (267) (268) (269) (270) (271) (272) (273) (274)
(283) (284) (285)
input CVBS
RTS0/1 HREF
(3) (2)
(3) (2)
VRLN = 1
RTS0/1 VREF
RTS0/1 VREF
VRLN = 0
81 × 2/LLC
RTS0/1 VS
RTS0/1 ODD
(4)
RTS0/1 V123
(3)
RTS0/1 FID
MHB337
(b) 2nd field
HREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.
ODD: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.
VS: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to 00 and/or RTSE13 to RTSE10 = BH.
V123: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.
VREF: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.
FID: selectable on RTS0 and/or RTS1 via I2C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.
(1) Line numbers in parenthesis refer to ITU line counting.
(2) VREF range short or long can be programmed via I2C-bus bit VRLN.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
(3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.
(4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the
field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of the slope is dependent on the internal
processing delay and may change a few clock cycles from version to version.
Fig.30 Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR
or fast mode (HTC = 01 or 11)].
1999 Jul 01
44
NXP [ NXP ]
