Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output timing (LLC); note 2
CL(LLC)
Tcy
δLLC
tr
output load capacitance
cycle time
15
35
40
−
−
−
−
−
−
40
39
60
5
pF
LLC
CL = 25 pF
ns
%
duty factors for tLLCH/tLLC
rise time LLC
ns
ns
tf
fall time LLC
−
5
Clock input timing (XTALI)
δXTALI
duty factor for tXTALIH/tXTALI nominal frequency
40
−
60
%
Horizontal PLL
fHn
nominal line frequency
50 Hz field
60 Hz field
−
−
−
15625
15734
−
−
Hz
Hz
%
−
∆fH/fHn
permissible static deviation
5.7
Subcarrier PLL
fSCn
nominal subcarrier
frequency
PAL BGHIN
−
−
−
−
4433619
3579545
3575612
3582056
−
−
−
−
−
−
Hz
Hz
Hz
Hz
Hz
NTSC M; NTSC-Japan
PAL M
combination-PAL N
∆fSC
lock-in range
±400
Crystal oscillator
fn
nominal frequency
3rd harmonic; note 3
−
−
24.576
−
MHz
10−6
∆f/fn
permissible nominal
frequency deviation
−
±50
∆Tf/fn(T)
permissible nominal
frequency deviation with
temperature
−
−
−
±20
10−6
CRYSTAL SPECIFICATION (X1)
Tamb(X1)
operating ambient
0
70
°C
temperature
CL
Rs
C1
C0
load capacitance
8
−
−
−
−
−
pF
Ω
series resonance resistor
motional capacitance
parallel capacitance
40
80
−
1.5 ±20%
3.5 ±20%
fF
−
pF
Notes
1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF.
2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to
drawings and conditions illustrated in Fig.26.
3. Order number: Philips 4322 143 05291.
1999 Jul 01
39
NXP [ NXP ]
