Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
phase detector input. The 2 bit SA register determines the selection
of the auxiliary phase detector signal.
accumulator works modulo Q. Q is preset by the serial control bit
FMOD to 8 when FMOD = “1”. Each time the accumulator
overflows, the feedback to the prescaler will select one cycle using
prescaler ratio R2 instead of R1.
Main Divider
The differential inputs are amplified (to internal ECL logic levels) and
provide excellent sensitivity (–20dBm at 1GHz) making the prescaler
ideally suited to directly interface to a VCO as integrated on the
SA620 RF gain stage, VCO and mixer device. The internal triple
modulus prescaler feedback loop FB controls the selection of the
divide by ratios 64/65/72, and reduces the minimum system division
ratio below the typical value required by standard dual modulus
(64/65) devices.
As shown above, this will increase the overall division ratio by 1 if
R2 = R1 + 1. The mean division ratio over Q main divider will then
be
NF
Q
NQ + N )
Programming a fraction means the prescaler with main divider will
divide by N or N + 1. The output of the main divider will be
modulated with a fractional phase ripple. This phase ripple is
proportional to the contents of the fractional accumulator FRD,
which is used for fractional current compensation.
This input stage is enabled when serial control bit EM = “1”.
Disabling means that all currents in the prescaler are switched off.
The main divider is built up by a 12 bit counter plus a sign bit.
Depending on the serial input values NM1, NM2, NM3, and the
prescaler select PR, the counter will select a prescaler ratio during a
number of input cycles according to Table 2 and Table 3.
Phase Detectors
The auxiliary and main phase detectors are a two D-type flip-flop
phase and frequency detector shown in Figure 8. The flip-flops are
set by the negative edges of output signals of the dividers. The
rising edge of the signal, L, will reset the flip-flops after both flip-flops
have been set. Around zero phase error this has the effect of
delaying the reset for 1 reference input cycle. This avoids
non-linearity or deadband around zero phase error. The flip-flops
drive on-chip charge pumps. A source current from the charge
pump indicates the VCO frequency will be increased; a sink current
indicates the VCO frequency will be decreased.
The loading of the work registers NM1, NM2, NM3 and PR is
synchronized with the state of the main counter, to avoid extra
phase disturbance when switching over to another main divider ratio
as explained in the Serial Input Programming section.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented with NF. The
10
1996 Aug 6
NXP [ NXP ]
