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SA7025DK 参数 Datasheet PDF下载

SA7025DK图片预览
型号: SA7025DK
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压1GHz的小数N分频合成器 [Low-voltage 1GHz fractional-N synthesizer]
分类和应用: 信号电路锁相环或频率合成电路光电二极管信息通信管理
文件页数/大小: 22 页 / 307 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
1GHz low-voltage Fractional-N synthesizer  
SA7025  
REFERENCE R  
MAIN N  
TIME  
VCO CYCLES  
N
N
N + 1  
N
N + 1  
DETECTOR  
OUTPUT  
2
4
1
3
0
CONTENTS  
ACCUM.  
FRACTIONAL  
COMPENSATION  
CURRENT  
PULSE-WIDTH  
MODULATION  
mA  
OUTPUT ON  
PHP, PHI  
µA  
PULSE-LEVEL  
MODULATION  
SR00608  
Figure 9. Waveforms for NF = 2, Fraction = 0.4  
PA registers. The f  
of the Auxiliary divider.  
signal can be used to verify the divide ratio  
Lock Detect  
AUX  
The output LOCK is H when the auxiliary phase detector AND the  
main phase detector indicates a lock condition. The lock condition  
is defined as a phase difference of less than +1 cycle on the  
reference input REF_IN. The lock condition is also fulfilled when the  
relative counter is disabled (EM = “0” or respectively EA = “0”) for  
the main, respectively auxiliary counter.  
If T1 = High and T0 = High, the lock output is configured as f  
The signal is the buffered output of the MAIN divider. The f  
signal appears as normally high and pulses low whenever the  
divider reaches terminal count from the value programmed into the  
NM1, NM2 or NM3 registers. The f signal can be used to verify  
.
MAIN  
MAIN  
MAIN  
the divide ratio of the MAIN divider and the prescaler.  
Test Modes  
The lock output is selectable as f  
, f  
, f  
and lock. Bits T1  
REF AUX MAIN  
and T0 of the E word control the selection (see Figures 6 and 10).  
If T1 = T0 = Low, or if the E-word is not sent, the lock output is  
configured as the normal lock output described in the Lock Detect  
section.  
If T1 = Low and T0 = High, the lock output is configured as f  
.
REF  
The signal is the buffered output of the reference divider NR and the  
3-bit binary counter SM. The f signal appears as normally low  
REF  
and pulses high whenever the divider reaches terminal count from  
the value programmed into the NR and SM registers. The f  
REF  
signal can be used to verify the divide ratio of the Reference divider.  
If T1 = High and T0 = Low, the lock output is configured as f  
.
AUX  
The signal is normally high and pulses low whenever the divider  
reaches terminal count from the value programmed into the NA and  
14  
1996 Aug 6