Philips Semiconductors
Product specification
1GHz low-voltage Fractional-N synthesizer
SA7025
DC ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
–3.35
–1.35
–20
I
RF
= –62.5µA;F
RD
= 1 to 7
13
I
RF
= –25µA;F
RD
= 1 to 7
–5.4
–2.15
–4.0
–1.6
TYP
–2.0
–1.0
MAX
–1.1
–0.5
20
–2.6
–1.05
UNITS
Fractional compensation PHP, speed up mode
1, 10
V
PHP
= V
DDA
, V
RN
= V
DDA
I
PHP_F_S
S
Fractional compensation output current
PHP vs F
RD3
Pump leakage
Fractional compensation PHI, speed up mode
1, 11
V
PHP
= V
DDA
/2, V
RN
= V
DDA
I
PHI_F
Fractional compensation output current
PHI vs F
RD3
Output leakage current PHP; normal
mode
1
Output leakage current PHI; normal
mode
1
Output leakage current PHA
µA
I
RF
= –62.5µA;F
RD
= 1 to 7
13
I
RF
= –25µA;F
RD
= 1 to 7
µA
nA
Charge pump leakage currents, charge pump not active
I
PHP_L
I
PHI_L
I
PHA_L
V
PHP
= 0.7 to V
DDA
– 0.8
V
PHI
= 0.7 to V
DDA
– 0.8
V
PHA
= 0.7 to V
DDA
– 0.8
0.1
0.1
0.1
10
10
10
nA
nA
nA
AC ELECTRICAL CHARACTERISTICS
V
DD
= V
DDA
= V
CCP
= 3V; T
A
= 25
°
C; f
RF_IN
= 1GHz, input level = –20dBm; unless otherwise specified.
Test Circuit, Figure 4. The parameters
listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
SYMBOL
Main divider
f
RF_IN
V
RF_IN
Input signal frequency
Input sensitivity
Direct coupled input
14
1000pF input coupling
1040MHz
2.7 < V
DD
and V
DDA
< 5.5V
2.7 < V
DD
and V
DDA
< 4.5V
2.7 < V
DD
and V
DDA
< 5.5V
2.7 < V
DD
and V
DDA
< 4.5V
500
300
100
3
0
4.5V
≤
V
DDA
≤
5.5V
4.5V
≤
V
DDA
≤
5.5V
0
0
0
200
100
3
10
30
30
30
B, C, D, E words
FVCO = 1030MHz
30
300
600
50
150
30
40
mV
P-P
kΩ
pF
MHz
ns
ns
ns
MHz
–20
1.04
1.04
0
25
30
GHz
dBm
PARAMETER
TEST CONDITIONS
LIMITS
MIN
TYP
MAX
UNITS
Reference divider (V
DD
= V
DDA
= 3V or V
DD
= 3V / V
DDA
= 5V)
f
REF_IN
V
REF_IN
Z
REF_IN
Input signal frequency
Input signal range, AC coupled
range
Reference divider input impedance
15
MHz
mV
P-P
kΩ
pF
Auxiliary divider
Input signal frequency
f
AUX_IN
PA = “0”, prescaler enabled
Input signal frequency
PA = “1”, prescaler disabled
V
AUX_IN
Z
AUX_IN
Input signal range, AC coupled
Auxiliary divider input impedance
Serial interface
15
f
CLOCK
t
SU
t
H
t
W
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
Hold time; CLOCK to DATA
Pulse width; CLOCK
Pulse width; STROBE
Main loop residual FM
In-Loop Performance
17
V
DDA
= 5V, V
DD
= 2.7V
R
MM
Hz
1996 Aug 6
6
PHILIPS [ NXP SEMICONDUCTORS ]
