Philips Semiconductors
Product specification
Dual P-channel enhancement
mode MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
Per P-channel
V
DS
V
GSO
I
D
I
DM
P
tot
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
open drain
T
s
≤
80
°C
note 1
T
s
= 80
°C;
note 2
T
amb
= 25
°C;
note 3
T
amb
= 25
°C;
note 4
T
amb
= 25
°C;
note 5
T
stg
T
j
I
S
I
SM
Notes
1. Pulse width and duty cycle limited by maximum junction temperature.
storage temperature
operating junction temperature
T
s
≤
80
°C
note 1
−
−
−
−
−
−
−
−
−65
−
−
−
−30
±20
PARAMETER
CONDITIONS
MIN.
PHP225
MAX.
UNIT
V
V
A
A
W
W
W
W
°C
°C
−2.3
−10
2
2
1
1.3
+150
150
−1.25
−5
Source-drain diode
source current (DC)
peak pulsed source current
A
A
2. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time.
3. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 27.5 K/W.
4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 90 K/W.
5. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with
an R
th a-tp
(ambient to tie-point) of 90 K/W.
1997 Jun 20
3
PHILIPS [ NXP SEMICONDUCTORS ]
