Philips Semiconductors
Product specification
Complementary enhancement mode
MOS transistors
PHC2300
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per FET
VDS
drain-source voltage (DC)
N-channel
−
−
−
300
V
V
V
P-channel
−300
±20
VGS
ID
gate-source voltage (DC)
drain current (DC)
N-channel
Ts = 80 °C; note 1
−
−
340
mA
mA
P-channel
−235
IDM
peak drain current
N-channel
note 2
−
−
−
−
−
−
1.4
A
P-channel
−0.9
1.6
A
Ptot
total power dissipation
Ts = 80 °C; note 3
W
W
W
W
°C
°C
Tamb = 25 °C; note 4
Tamb = 25 °C; note 5
Tamb = 25 °C; note 6
1.8
0.9
1.2
Tstg
Tj
storage temperature
−55
−55
+150
+150
operating junction temperature
Notes
1. Ts is the temperature at the soldering point of the drain leads.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. (So both devices may be loaded up to 1.6 W at the same time).
4. Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an Rth a-tp (ambient
to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an Rth a-tp (ambient
to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Value based on a printed-circuit board with
an Rth a-tp (ambient to tie-point) of 90 K/W.
1997 Oct 24
3
NXP [ NXP ]
