PDIUSBD12
USB interface device with parallel bus
Philips Semiconductors
t
t
RHSH
AHRH
DMREQ
DMACK_N
t
SHAH
RD_N/WR_N
t
EL
(1)
EOT_N
SV00874
EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW.
Fig 19. Single-cycle DMA timing.
t
RHSH
DMREQ
t
SLRL
DMACK_N
t
SHAH
RD_N/WR_N
SV00875
Fig 20. Burst DMA timing.
Fig 21. DMA terminated by EOT.
9397 750 09238
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Product data
Rev. 08 — 20 December 2001
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