Philips Semiconductors
Product specification
I
2
C-bus controller
6.8.2.7
BB
6.11.1
D
ELETED FUNCTIONS
PCF8584
‘Bus Busy’ bit. This is a read-only flag indicating when the
I
2
C-bus is in use. A zero indicates that the bus is busy, and
access is not possible. This bit is set/reset (logic 1/logic 0)
by STOP/START conditions.
6.9
Multi-master operation
The following functions are not available in the PCF8584:
•
Always selected (ALS flag)
•
Access to the bit counter (BC0 to BC2)
•
Full SCL frequency selection (2 bits instead of 5 bits)
•
The non-acknowledge mode (ACK flag)
•
Asymmetrical clock (ASC flag).
6.11.2
ADDED FUNCTIONS
To avoid conflict between data and repeated START and
STOP operations, multi-master systems have some
limitations:
•
When powering up multiple PCF8584s in multi-master
systems, the possibility exists that one node may power
up slightly after another node has already begun an
I
2
C-bus transmission; the Bus Busy condition will thus
not have been detected. To avoid this condition, a delay
should be introduced in the initialization sequence of
each PCF8584 equal to the longest I
2
C-bus
transmission, see flowchart ‘PCF8584 initialization’
(Fig.5).
6.10
Reset
The following functions either replace the deleted
functions or are completely new:
•
Chip clock prescaler
•
Assert acknowledge bit (ACK flag)
•
Register selection bits (ES1 and ES2 flags)
•
Additional status flags (BER, ‘bus error’)
•
Automatic interface control between 80XX and
68000-type microcontrollers
•
Programmable interrupt vector
•
Strobe generator
•
Bus monitor function
•
Long-distance mode [non-I
2
C-bus mode (4-wire); only
for communication between parallel-bus processors
using the PCF8584 at each interface point].
6.12
6.12.1
Special function modes
S
TROBE
A LOW level pulse on the RESET (CLK must run) input
forces the I
2
C-bus controller into a well-defined state.
All flags in S1 are reset to logic 0, except the PIN flag and
the BB flag, which are set to logic 1. S0' and S3 are set
to 00H.
The RESET pin is also used for the STROBE output
signal. Both functions are separated on-chip by a digital
filter. The reset input signal has to be sufficiently long
(minimum 30 clock cycles) to pass through the filter.
The STROBE output signal is sufficiently short (8 clock
cycles) to be blocked by the filter. For more detailed
information on the strobe function see Section 6.12.
6.11
Comparison to the MAB8400 I
2
C-bus interface
The structure of the PCF8584 is similar to that of the
MAB8400 series of microcontrollers, but with a modified
control structure. Access to all I
2
C-bus control and status
registers is done via the parallel-bus port in conjunction
with register select input A0, and control bits ESO, ES1
and ES2.
When the I
2
C-bus controller receives its own address (or
the ‘00H’ general call address) followed immediately by a
STOP condition (i.e. no further data transmitted after the
address), a strobe output signal is generated at the
RESET/STROBE pin (pin 19). The STROBE signal
consists of a monostable output pulse (active LOW),
8 clock cycles long (see Fig.9). It is generated after the
STOP condition is received, preceded by the correct slave
address. This output can be used as a bus access
controller for multi-master parallel-bus systems.
1997 Oct 21
13
PHILIPS [ NXP SEMICONDUCTORS ]
