Philips Semiconductors
Product specification
I
2
C-bus controller
PCF8584
andbook, full pagewidth
to/from microcontroller parallel bus
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
I
2
C-Bus
to/from
SDA line
Read Buffer
Data Shift Register S0 and Read Buffer
Shift register
Read
only
Write
only
MBE705
Fig.4 Data shift register/bus buffer S0.
In receiver mode the data from the shift register is copied to the read buffer during the acknowledge phase. Further
reception of data is inhibited (SCL held LOW) until the S0 read buffer is read (see Section 6.8.1.1).
In the transmitter mode data is transmitted to the I
2
C-bus as soon as it is written to the S0 shift register if the serial I/O is
enabled (ESO = 1).
Remarks:
1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the
I
2
C-bus controller operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies.
2. To start a read operation immediately after a write, it is necessary to read the S0 read buffer in order to invoke
reception of the first byte (‘dummy read’ of the address). Immediately after the acknowledgement, this first byte will
be transferred from the shift register to the read buffer. The
next
read will then transfer the correct value of the first
byte to the microcontroller bus (see Fig.7).
6.8
Control/status register S1
Register S1 controls I
2
C-bus operation and provides I
2
C-bus status information. Register S1 is accessed by a HIGH
signal on register select input A0. For more efficient communication between microcontroller/processor and the I
2
C-bus,
register S1 has separate read and write functions for all bit positions (see Fig.3). The write-only section provides register
access control and control over I
2
C-bus signals, while the read-only section provides I
2
C-bus status information.
Table 4
Control/status register S1
BITS
PIN
PIN
ESO
0
(3)
ES1
STS
ES2
BER
ENI
AD0/LRB
STA
AAS
STO
LAB
ACK
BB
MODE
write only
read only
CONTROL/STATUS
Control
(1)
Status
(2)
Notes
1. For further information see Section 6.8.1.
2. For further information see Section 6.8.2.
3. Logic 1 if not-initialized.
1997 Oct 21
9
PHILIPS [ NXP SEMICONDUCTORS ]
