Philips Semiconductors
Product specification
I
2
C-bus controller
PCF8584
handbook, full pagewidth
A0 = HIGH
A0 = LOW
enables data transfer to/from
register S1
Access to all other registers
defined by the bit pattern in
register S1
START
power-on
address line A0
reset minimum
30 clock cycles
PCF8584 resets to
slave receiver mode
send byte 80H
parallel bus interface
determined by
PCF8584 (80XX/68XXX)
send byte 55H
A0 = HIGH
send byte A0H
A0 = LOW
send byte 1CH
A0 = HIGH
send byte C1H
Loads byte C1H into register S1; register enable
serial interface, set I
2
C-bus into idle mode;
SDA and SCL are HIGH. The next write or read
operation will be to/from data transfer register
S0 if A0 = LOW.
On power-on, if an PCF8584 node is powered-up
slightly after another node has already begun an
I
2
C-bus transmission, the bus busy condition will
not have been detected. Thus, introducing this
delay will insure that this condition will not occur.
MBE714
A0 = HIGH
Loads byte 80H into register S1'
i.e. next byte will be loaded into register S0'
(own address register); serial interface off.
A0 = LOW
Loads byte 55H into register S0';
effective own address becomes AAH.
Loads byte A0H into register S1, i.e. next byte
will be loaded into the clock control register S2.
Loads byte 1CH into register S2;
system clock is 12 MHz; SCL = 90 kHz.
delay: wait a time
equal to the longest I
2
C
message to synchronize
BB-bit. (multimaster
systems only
initialization of
PCF8584 completed
END
Fig.5 PCF8584 initialization sequence.
1997 Oct 21
15
PHILIPS [ NXP SEMICONDUCTORS ]
