Philips Semiconductors
Product specification
I
2
C-bus controller
6.12.2
L
ONG
-
DISTANCE MODE
•
The controller is always selected.
PCF8584
The long-distance mode provides the possibility of
longer-distance serial communication between parallel
processors via two I
2
C-bus controllers. This mode is
selected by setting ES1 to logic 1 while the serial interface
is enabled (ESO = 1).
In this mode the I
2
C-bus protocol is transmitted over
4 unidirectional lines, SDA OUT, SCL IN, SDA IN and
SCL IN (pins 2, 3, 4 and 5). These communication lines
should be connected to line drivers/receivers
(example: RS422) for long-distance applications.
Hardware characteristics for long-distance transmission
are then given by the chosen standard. Control of data
transmission is the same as in normal I
2
C-bus mode. After
reading or writing data to shift register S0, long-distance
mode must be initialized by setting ESO and ES1 to
logic 1. Because the interrupt output INT is not available in
this operating mode, synchronization of data
transmission/reception must be polled via the PIN bit.
Remarks:
Before entering the long-distance mode, ENI must be
set to logic 0.
When powering up an PCF8584-node in long-distance
mode, the PCF8584 must be isolated from the 4-wire
bus via 3-state line drivers/receivers until the PCF8584
is properly initialized for long-distance mode. Failure to
implement this precaution will result in system
malfunction.
6.12.3
M
ONITOR MODE
•
The controller is always in the slave receiver mode.
•
The controller never generates an acknowledge.
•
The controller never generates an interrupt request.
•
A pending interrupt condition does not force SCL LOW.
•
BB is set to logic 0 after detection of a START condition,
and reset to logic 1 after a STOP condition.
•
Received data is automatically transferred to the read
buffer.
•
Bus traffic is monitored by the PIN bit, which is reset to
logic 0 after the acknowledge bit of an incoming byte has
been received, and is set to logic 1 as soon as the first
bit of the next incoming byte is detected. Reading the
data buffer S0 sets the PIN bit to logic 1. Data in the read
buffer is valid from PIN = 0 and during the next 8 clock
pulses (until next acknowledge).
•
AAS is set to logic 1 at every START condition, and
reset at every 9th clock pulse.
7
7.1
SOFTWARE FLOWCHART EXAMPLES
Initialization
The flowchart of Fig.5 gives an example of a proper
initialization sequence of the PCF8584.
7.2
Implementation
When the 7-bit own address register S0' is loaded with all
zeros, the I
2
C-bus controller acts as a passive I
2
C monitor.
The main features of the monitor mode are:
The flowcharts (Figs 6 to 9) illustrate proper programming
sequences for implementing master transmitter, master
receive, and master transmitter, repeated start and master
receiver modes in polled applications.
1997 Oct 21
14
PHILIPS [ NXP SEMICONDUCTORS ]
