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SCL
SDA
1
2
3
4
5
6
7
8
9
P0x
P1x
P0x
P1x
S
0
1
0
0
A2 A1 A0
1
A
DATA 00
A
DATA 11
A
DATA 00
A
DATA 12
1
P
START condition
R/W
acknowledge
from master
acknowledge
from master
acknowledge
from master
no acknowledge
from master
acknowledge
from slave
read from port 0
data into port 0
read from port 1
DATA 00
DATA 10
data into port 1
INT
DATA 11
DATA 12
t
t
d(rst)
002aab810
v(D)
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).
Fig 15. Read input port register, scenario 1
NXP [ NXP ]
