Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC573A
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00399
FUNCTION TABLE
INPUTS
LE
OUTPUTS
OPERATING MODES
INTERNAL LATCHES
OE
D
Q to Q
n
0
7
Enable and read register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
Latch and read register
L
L
L
L
l
h
L
H
L
H
Latch register and
disable outputs
H
H
L
L
l
h
L
H
Z
Z
H
h
L
l
X
Z
= HIGH voltage level
= HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition
= LOW voltage level
= LOW voltage level one setup time prior to the HIGH-to-LOW LE transition
= Don’t care
= High impedance OFF-state
4
1998 Jul 29
NXP [ NXP ]
