Objective specification
Rev. 02 — 23 October 2000
3 of 73
9397 750 07648
5. Block diagram
Philips Semiconductors
to/from USB
D+
D−
12 MHz
CS0, CS1,
DA0
*
, DA1
*
, DA2
5
18, 17,
19, 20, 21
DMA
HANDLER
DREQ, DACK,
DIOR, DIOW
4
12, 13,
14, 15
11
16
EOT
INTRQ
IORDY
*
XTAL1
6
5
60
XTAL2
59
3.3 V
40× PLL
OSCILLATOR
BIT CLOCK
RECOVERY
1.5
kΩ
RPU 7
SoftConnect
DMA
INTERFACE
22
40, 41,
44 to 57
MEMORY
MANAGEMENT
UNIT
19
DMA
REGISTERS
20, 9
16
DATA0 to DATA15
2
BUS_CONF
*
MODE0
*
, MODE1
RREF 8
12.2 kΩ
(±0.1%)
USB 2.0
TRANSCEIVER
PHILIPS
SIE
22
INTEGRATED
RAM
(8 KBYTE)
MICRO-
CONTROLLER
HANDLER
MICRO
CONTROLLER
INTERFACE
38, 39, 30 to 35
25, 29, 26, 27
8
AD0 to AD7
4
CS, ALE/A0, (R/W)/RD,
DS/WR
READY
*
RESET
10
POWER-ON
RESET
internal
reset
VCC(5.0)
4
2, 37,
43, 64
5V
3.3 V
VOLTAGE
REGULATORS
3.3 V
digital
supply
analog
supply
28
SYSTEM
CONTROLLER
INT
ISP1581
1, 36, 42, 61
4
DGND
3, 23
2
AGND
4
24, 58
2
63
62
MGT234
VCC(3.3)
Vreg(3.3)
SUSPEND
WAKEUP
*
Denotes shared pin usage
USB 2.0 HS interface device
© Philips Electronics N.V. 2000. All rights reserved.
ISP1581
The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Configuration register).
Fig 1. Block diagram.
PHILIPS [ NXP SEMICONDUCTORS ]
