ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
t
A0WL
A0
T
cy(RW)
t
WHSH
CS
]
t
t
RHDZ
RLDV
t
[
data
(read) AD 7:0
address
t
RLRH
RHSH
RD
t
AVWH
t
WHRH
WR
t
WHDZ
[
]
(write) AD 7:0
data
address
t
DVWH
t
WLWH
WR
(I2)
t
WHWH
RD
(I1)
004aaa011
Fig 19. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 = 1).
Table 76: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 1)
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Reading
tRLDV
Parameter
Min
Max
Unit
RD LOW to data valid delay
RD HIGH to data outputs three-state delay
RD HIGH to CS HIGH delay
RD LOW pulse width
-
26
15
-
ns
ns
ns
ns
ns
tRHDZ
0
tRHSH
0
tRLRH
>tRLDV
40
-
tWHRH
Writing
tA0WL
WR/DS HIGH to RD HIGH delay
-
A0 set-up time before WR/DS LOW
address set-up time before WR/DS HIGH
data set-up time before WR/DS HIGH
data hold time after WR/DS HIGH
WR/DS HIGH to CS HIGH delay
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tAVWH
5
tDVWH
5
tWHDZ
5
tWHSH
tWLWH
tWHWH
General
Tcy(RW)
tI2HI1X
0
WR/DS LOW pulse width
15
40
WR/DS HIGH (address) to WR/DS HIGH (data) delay
read/write cycle time
80
5
-
-
ns
ns
R/W hold time after DS HIGH
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
59 of 79
NXP [ NXP ]
