ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
t
t
t
WHSH
LLSH
SLWL
CS
ALE
WR
RD
004aaa277
t
SLRL
t
RHSH
Fig 16. Set-up and hold time.
Table 75: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 0)
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Reading
tRLRH
Parameter
Min
Max
Unit
RD LOW pulse width
>tRLDV
-
ns
ns
ns
ns
ns
tRLDV
RD LOW to data valid delay
-
25
15
-
tRHDZ
RD HIGH to data outputs three-state delay
RD HIGH to CS HIGH delay
0
0
0
tRHSH
tLLRL
ALE LOW set-up time before RD LOW
-
Writing
tWLWH
tDVWH
tLLWL
WR/DS LOW pulse width
15
5
-
-
-
-
-
ns
ns
ns
ns
ns
data set-up time before WR HIGH
ALE LOW to WR/DS LOW delay
data hold time after WR/DS HIGH
WR/DS HIGH to CS HIGH delay
0
tWHDZ
tWHSH
General
Tcy(RW)
tAVLL
5
0
read/write cycle time
80
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
address set-up time before ALE LOW
R/W set-up time before ALE LOW
ALE LOW to DS LOW delay
R/W hold time after DS HIGH
ALE LOW to CS HIGH
tI1VLL
5
tLLI2L
5
tI2HI1X
tLLSH
5
0
tSLWL
CS LOW to WR LOW
0
tSLRL
CS LOW to RD LOW
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
56 of 79
NXP [ NXP ]
