ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 49: Task File register 3F6 (address: 4EH): bit allocation
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L.
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
alternate status/command (ATA or ATAPI)
00H
00H
R/W
Bus reset
Access
Table 50: Task File register 3F7 (address: 4FH): bit allocation
CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H.
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
drive address (ATA) or reserved (ATAPI)
00H
00H
R/W
Bus reset
Access
9.4.7 DMA Interrupt Reason register (address: 50H)
This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed
after a DMA command has been executed. An interrupt source is cleared by writing a
logic 1 to the corresponding bit. The bit allocation is given in Table 51.
Table 51: DMA Interrupt Reason register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
ODD_IND
EXT_EOT
INT_EOT
INTRQ_
DMA_
PENDING XFER_OK
Reset
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
Bus reset
Access
Bit
0
R/W
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
0
Symbol
1F0_WF_E 1F0_WF_F 1F0_RF_E READ_1F0
BSY_
DONE
TF_RD_
DONE
CMD_
INTRQ_OK
reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
Bus reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 52: DMA Interrupt Reason Register: bit description
Bit
Symbol
Description
15 to 13 -
reserved
12
ODD_IND
A logic 1 indicates that the last packet with odd bytes has
been transferred from the OUT token buffer to the DMA. This
is applicable only for the OUT token data in the DMA slave
mode. It has no meaning for the IN token data. Refer to the
document Using the Odd Bit Indicator for DMA.
11
10
EXT_EOT
INT_EOT
A logic 1 indicates that an external EOT is detected. This is
applicable only in GDMA slave mode.
A logic 1 indicates that an internal EOT is detected. see
Table 53.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
40 of 79
NXP [ NXP ]
