ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 36: DMA Hardware register: bit description
Bit
Symbol
Description
7 to 6
ENDIAN[1:0] These bits determine whether the data bus is swapped between
internal RAM and the DMA bus: This only applies for modes
GDMA (slave) and MDMA (master):
00H — normal data representation
16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]
01H — swapped data representation
16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]
02H, 03H — reserved.
Note: while operating with 8 bit data bus, ENDIAN bits should be
always set to 00H.
5
EOT_POL
Selects the polarity of the End Of Transfer input (used in GDMA
slave mode only):
0 — EOT is active LOW
1 — EOT is active HIGH.
4
3
2
1
0
MASTER
Selects the DMA master/slave mode:
0 — GDMA slave mode.
1 — MDMA master mode.
ACK_POL
DREQ_POL
Selects the DMA acknowledgement polarity:
0 — DACK is active LOW
1 — DACK is active HIGH.
Selects the DMA request polarity:
0 — DREQ is active LOW
1 — DREQ is active HIGH.
WRITE_POL Selects the DIOW strobe polarity:
0 — DIOW is active LOW
1 — DIOW is active HIGH.
READ_POL
Selects the DIOR strobe polarity:
0 — DIOR is active LOW
1 — DIOR is active HIGH.
9.4.5 DMA Strobe Timing register (address: 60H)
This 1-byte register controls the strobe timings for the MDMA mode, when the
DMA_MODE bits in the DMA Configuration register have been set to 03H. The bit
allocation is given in Table 37.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
36 of 79
NXP [ NXP ]
