ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 58: Interrupt register: bit description…continued
Bit
9
Symbol
Description
reserved
EP0SETUP
reserved.
8
A logic 1 indicates that a SETUP token was received on
Endpoint 0.
7
6
reserved
DMA
reserved.
DMA status: A logic 1 indicates a change in the DMA Status
register.
5
HS_STAT
High Speed Status:.A logic 1 indicates a change from FS to
HS mode (HS connection). This bit is not set, when the system
goes into a FS suspend.
4
3
2
RESUME
SUSP
Resume status: A logic 1 indicates that a status change from
‘suspend’ to ‘resume’ (active) was detected.
Suspend status: A logic 1 indicates that a status change from
active to ‘suspend’ was detected on the bus.
PSOF
Pseudo SOF interrupt: A logic 1 indicates that a Pseudo SOF
or µSOF was received. Pseudo SOF is an internally generated
clock signal (FS: 1 ms period, HS: 125 µs period) synchronized
to the USB bus SOF/µSOF.
1
0
SOF
SOF interrupt: A logic 1 indicates that a SOF/µSOF was
received.
BRESET
Bus Reset: A logic 1 indicates that a USB bus reset was
detected.
9.5.2 Chip ID register (address: 70H)
This read-only register contains the chip identification and the hardware version
numbers. The firmware should check this information to determine the functions and
features supported. The register contains 3 bytes and the bit allocation is shown in
Table 59.
Table 59: Chip ID register: bit allocation
Bit
23
15
7
22
14
6
21
13
5
20
19
18
10
2
17
16
Symbol
Reset
CHIPID[23:16]
15H
15H
R
Bus reset
Access
Bit
12
11
9
8
Symbol
Reset
CHIPID[15:8]
81H
81H
R
Bus reset
Access
Bit
4
3
1
0
Symbol
Reset
VERSION[7:0]
51H
51H
R
Bus reset
Access
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
44 of 79
NXP [ NXP ]
