ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
All data IN transactions use the Transmit buffers (TX), which are handled by the
DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which
are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,
OUT and SETUP) are handled by the CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, Setup and High-Speed Status) can also be controlled individually. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in
Table 12.
Table 12: Interrupt Enable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
reserved
IEP7TX
IEP7RX
-
-
-
-
-
-
-
0
0
Bus Reset
Access
Bit
-
-
-
-
-
0
R/W
17
0
R/W
16
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
Symbol
Reset
IEP6TX
IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX
IEP3TX
0
IEP3RX
0
0
0
0
0
0
0
Bus Reset
Access
Bit
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9
R/W
8
15
14
13
12
11
10
Symbol
Reset
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
reserved IEP0SETUP
0
0
0
0
0
0
-
0
Bus Reset
Access
Bit
0
0
R/W
6
0
0
0
0
-
R/W
1
0
R/W
R/W
R/W
R/W
R/W
R/W
7
5
4
3
2
0
Symbol
Reset
reserved
IEDMA
0
IEHS_STA
IERESM
IESUSP
IEPSOF
IESOF
0
IEBRST
0
-
-
0
0
0
0
0
0
0
0
Bus Reset
Access
0
0
unchanged
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 13: Interrupt Enable register: bit description
Bit
Symbol
Description
reserved; must write logic 0
31 to 26
25 to 12
-
IEP7TX to
IEP1RX
A logic 1 enables interrupt from the indicated endpoint.
11
10
9
IEP0TX
IEP0RX
-
A logic 1 enables interrupt from the Control IN endpoint 0.
A logic 1 enables interrupt from the Control OUT endpoint 0.
reserved
8
IEP0SETUP
A logic 1 enables the interrupt for the Setup data received on
endpoint 0.
7
-
reserved
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
21 of 79
NXP [ NXP ]
