ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 15: Endpoint Index register: bit description
Bit
7 to 6
5
Symbol
Description
-
reserved
EP0SETUP
Selects the SETUP buffer for Endpoint 0:
0 — EP0 data buffer
1 — SETUP buffer.
Must be logic 0 for access to other endpoints than Endpoint 0.
4 to 1
0
ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access
of Buffer Length, Control Function, Data Port, Endpoint Type,
MaxPacketSize and Short Packet.
DIR
Direction bit: Sets the target endpoint as IN or OUT endpoint:
0 — target endpoint refers to OUT (RX) FIFO
1 — target endpoint refers to IN (TX) FIFO.
Table 16: Addressing of Endpoint 0 buffers
Buffer name
SETUP
EP0SETUP
ENDPIDX
00H
DIR
0
1
0
0
Data OUT
Data IN
00H
0
00H
1
9.3.2 Control Function register (address: 28H)
The Control Function register is used to perform the buffer management on the
endpoints. It consists of 1 byte and the bit configuration is given in Table 17.The
register bits can stall, clear or validate any enabled data endpoint. Before accessing
this register, the Endpoint Index register must be written first to specify the target
endpoint.
Table 17: Control Function register: bit allocation
Bit
7
6
5
4
CLBUF
0
3
VENDP
0
2
1
0
STALL
0
Symbol
Reset
reserved
reserved
STATUS[1]
-
-
-
-
-
-
-
-
0
0
Bus reset
Access
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1] Only applicable for control IN/OUT.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
23 of 79
NXP [ NXP ]
